1. Field of the Invention
The present invention relates to technology for an interface circuit which is connected to a signal line reaching an intermediate potential when a signal transmitted from an external circuit attains an inactive state, more particularly to an interface circuit which is connected to a signal for transmitting a strobe signal from a double data rate synchronous dynamic random access memory (DDR SDRAM).
2. Description of Related Art
In the reading action of the DDR SDRAM, data is outputted to a memory bus from the DDR SDRAM synchronously with an edge of a data strobe signal DQS. When at this time the data strobe signal is in an inactive state, the output side terminal attains a high impedance state. A terminal resistor is connected to a signal line for transmitting the data strobe signal DQS and when the output side terminal attains a high impedance state, the potential of the signal line adopts an intermediate potential on the basis of a proportional division of the terminal resistor in terms of the velocity of transition of the state of the data strobe signal DQS.
On the other hand, a device for acquiring data outputted onto a memory bus synchronously with an edge of the data strobe signal DQS needs to acquire data by means of the data strobe signal DQS in a state other than the intermediate potential, that is, in an active state of either logic-high level or a logic-low level. A signal line at an intermediate potential maintains its potential with only the terminal resistor, so that a level of signal is likely to become unstable because common noise is also present. If a data strobe signal DQS in such a state is used as a clock for acquisition of data, there is a real danger that acquisition errors will occur.
A requirement for avoiding this problem is to detect that the signal line for transmitting the data strobe signal DQS is at an intermediate potential, and, in accordance with the results of such a detection, to interrupt propagation of a signal from the signal line.
In order to detect the state of a signal line for transmitting the data strobe signal DQS, that is, to detect whether or not the signal line is at an intermediate potential, one possibility is to adopt the technology of a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Publication No. H9(1997)-213884.
FIG. 9 illustrates a circuit diagram showing an input buffer portion 152 in the semiconductor integrated device disclosed in the Japanese Unexamined Patent Publication No. H9(1997)-213884.
By means of comparing with reference voltage Vref the potential of signal lines a and b for transmitting signals that have been inputted from outside, and that are of a level complementary to each other, the input buffer portion 152 can detect whether or not the output terminal which drives signal lines a and b is in a high impedance state.
When this semiconductor integrated device detects that the output terminal of the input buffer portion 152 is in a high impedance state, propagation of signals transmitted through the signal lines a and b, and in accordance with the results of the detection, is interrupted. Consequently, malfunctioning of a circuit can be prevented at a subsequent stage in which used a signal transmitted through signals lines a and b are as an acquisition clock.